Hi oli, good to find you here!
I can’t give exact answers to your questions because the code is not yet finalised, but I’ll try to give an indication -
The chip we are looking at is the STM32F4 ARM Cortex M4 which has three separate memory regions, totalling 192kB SRAM. Almost all of the general purpose SRAM, which is 112kB, will be available for patches, and some of the CCM can be used for buffers.
We’d like to reach the external memory push target, which opens up much greater possibilities for delay lines and long verbs.
Block size is likely to be configurable, as is the sampling frequency.
As for performance, the example we use is a 7-band EQ which can be implemented in 299 cycles per sample, and the processor is capable of more than 3500 cycles per sample at 48kHz. The Cortex M4 can do many complex instructions like Multiply and Accumulate, and 32bit floating point, in single cycles, and has SIMD support which makes it possible to do two 16-bit instructions in one cycle. It’s a very nice little chip!
hth,
Martin